This invention relates generally to field effect semiconductor devices and methods for making such devices. More particularly this invention relates to narrow channel, low current field effect transistors (FETs) and methods for making such transistors.
Currently there is considerable research and development activity in the semiconductor industry directed toward insulated gate field effect transistors (IGFETs). One current thrust of developments in this area is to form larger numbers of IGFET devices on each semiconductor integrated circuit (IC) chip. Obviously, to form more IGFET devices per unit of chip area it is necessary to shrink the size of each device. To shrink the size of an IGFET device, it is necessary to reduce either the width or the length of each device or, preferably, both. All other parameters being equal, the drain-to-source current of a field effect transistor is proportional to the width-to-length ratio (W/L) of the device channel. Accordingly, if the channel length of IGFET devices alone is reduced to enable more devices per unit area to be formed, the amount of current drawn by each device increases. Correspondingly, the overall power dissipation of an integrated circuit chip incorporating a larger number of such shorter channel devices goes up dramatically. Thus, the semiconductor technologist faces the problem of dealing with increased power dissipation if he reduces the size of his IGFET devices by shrinking only the channel length.
Power dissipation per device can be kept constant by shrinking the width of the device in the same ratio as the length of the device. However, the lower limit on channel width is conventionally determined by the resolution of the lithography technique employed in fabricating the device. While highly sophisticated new methods of lithography, using electron beams and x-rays in order to achieve smaller device dimensions, are being developed, the equipment required is very expensive, especially if high volume production is desired. Consequently, the majority of ICs today are still being manufactured using conventional photolithography with ultraviolet-sensitive photoresists and contact or projection photomask aligning equipment. Typically, the limit of resolution of such conventional photolithography is in the vicinity of about three microns, with a maximum mask alignment error of about one micron.
Jones and Van Velthoven patent application Ser. No. 890,425, filed Mar. 27, 1978 now U.S. Pat. No. 4,212,638, and assigned to NCR Corporation discloses a method of fabricating low current depletion load devices (or other IGFET devices types) involving narrow (approximately 0.1 micron) device channels. For purposes of this discussion, the term "narrow" will be used to denote a width which is substantially less than the minimum photolithographic feature size (e.g. the three microns mentioned above). The method taught in the Jones et al. patent essentially comprises the formation of a window or well in an oxide masking structure formed on the semiconductor substrate, performing an enhancement implant in the substrate region in the well, enlarging the well by etching the oxide a controlled amount to expose a narrow region of the substrate around the periphery of the implanted enhancement section, performing a depletion implant in the substrate to form narrow depletion channel regions flanking the central enhancement channel region, and then forming a single conductor-insulator gate structure over both the narrow channel regions and the central channel region. The two narrow channel regions (0.1 micron combined width) form a depletion device with an effective channel width substantially less than the minimum photolithographic feature size of about three microns. Using other implant-type combinations, other combinations of enhancement and/or depletion channel devices are possible using the Jones et al. approach.
Sefick and Jones U.S. Pat. No. 4,145,233, issued Mar. 20, 1979 to NCR Corporation discloses an alternative method for forming the same type of low current IGFET device as taught in the Jones et al. patent referred to above. The method disclosed in the Sefick et al. patent is the formation of a photoresist mask on a masking oxide layer disposed on the semiconductor substrate; overetching the oxide under the photoresist mask to produce an oxide mask aperture larger than the photoresist mask aperture; forming the central enhancement section by ion implantation through the photoresist mask aperture; removing the photoresist mask and performing a second ion implantation through the slightly larger oxide mask aperture to form narrow depletion channel regions flanking the central enhancement channel region; and then forming a single conductor-insulator gate structure over both narrow channel regions and the central channel region.